1. Field of the Invention
The present invention relates to a semiconductor memory cell, specifically, a thin film transistor having an electric charge accumulating layer. The present invention also relates to a semiconductor memory device in which a thin film transistor having an electric charge accumulating layer and a thin film transistor are formed on a substrate having an insulating surface.
2. Description of the Related Art
EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory are known as representatives of semiconductor non-volatile memories. Unlike major semiconductor memories such as DRAM (Dynamic Random Access Memory) and SRAM (static RAM), EEPROM and flash memory do not lose data when power is turned off since they are non-volatile. They are also superior to magnetic disc, which is another representative non-volatile memory, in such characteristics as high integration degree, withstandingness against impact, small power consumption, and high writing/reading speed.
Semiconductor non-volatile memories thus have characteristics suitable for portable machines, and their application to portable machines is being developed. In particular, flash memory having high integration degree is widely applied and, recently, multi-valued memories with even higher integration degree have begun to appear on the market. These are of course non-volatile memories on single crystal silicon substrates.
On the other hand, popularization of cellular phones and other portable machines having display units has brought an increasing demand for system on panel in which a display portion and a logic circuit portion are integrally formed on a substrate having an insulating surface. With this trend, techniques for manufacturing a non-volatile memory on a substrate having an insulating surface are now needed.
In manufacturing a non-volatile memory on a substrate having an insulating surface, one conceivable mode is to construct a memory cell array from semiconductor memory cells and use thin film transistors (hereinafter referred to as TFTs) for peripheral circuits such as a decoder circuit for selecting a memory cell and a writing/reading circuit.
The term semiconductor memory cell in the present invention refers to a thin film transistor that has an electric charge accumulating layer surrounded by an insulating film between a semiconductor active layer and a gate electrode. For example, the term covers a thin film transistor having a structure with a floating gate electrode, or an MNOS structure, or an MONOS structure.
For a non-volatile memory as such, important objectives are improvement in reliability of a semiconductor memory cell which is lowered as electric charges are injected to and discharged from its electric charge accumulation layer and improvement of the total operation speed of the memory cell array and the peripheral circuits.
First, regarding the reliability, a semiconductor memory cell has the following structural problem. Shown in FIGS. 2A to 2C are the structure of a typical semiconductor memory cell manufactured on a substrate having an insulating surface. FIG. 2A is a plan view thereof whereas FIGS. 2B and 2C are its sectional view in the channel length direction (sectional view of Axe2x80x94Axe2x80x2) and sectional view in the channel width direction (sectional view of Bxe2x80x94Bxe2x80x2), respectively. In the semiconductor memory cell of FIGS. 2A to 2C, a semiconductor active layer 202, a first gate insulating film 203, a floating gate electrode 204, a second gate insulating film 205, and a control gate electrode 206 are layered on a substrate 201 having an insulating surface. The semiconductor active layer 202 is composed of a channel region 207 and high concentration impurity regions 208 that are doped with an impurity of one conductivity type.
The floating gate electrode 204 is one mode of the electric charge accumulating layer. One of the high concentration impurity regions 208 may partially overlap the floating gate electrode 204 with the first gate insulating film 203 sandwiched therebetween.
In this semiconductor memory cell structure, what causes a problem regarding the reliability is the shape of a semiconductor active layer end 209. With the semiconductor active layer shaped as shown in FIGS. 2A to 2C, the electric field concentrates on a corner of the semiconductor active layer end when the control gate electrode and the active layer have different electric potentials. This causes local injection/discharge of electric charges in the semiconductor active layer end 209. As a result, the first gate insulating film is degraded intensively in the semiconductor active layer end 209 and the reliability is lowered.
In order to prevent local degradation of the first gate insulating film due to the electric field concentration, it is effective to invent a semiconductor memory cell structure that does not have a region where the electric field concentrates as the semiconductor active layer end 209.
As to improvement of the memory operation speed, it is important to manufacture high performance TFTs and semiconductor memory cells on a substrate having an insulating surface.
The technology of forming a TFT on a substrate having an insulating surface has made great advances mainly through research and development of semiconductor display devices (typically, liquid crystal display devices and EL display devices). For instance, TFTs using polycrystalline silicon films have higher field effect mobility (also called mobility) than TFTs formed from amorphous silicon films and thus have enabled a driving circuit on the same substrate where pixels are formed to control a display portion, which in the past was performed by a driving circuit external to the substrate.
With system on panel looming on horizon, the operation speed has to be increased even more and TFTs of higher performance are demanded.
One of techniques for forming a TFT on a substrate having an insulating surface that has been attracting attention in recent years is manufacture of a crystalline semiconductor film by laser light irradiation. For laser oscillation apparatus, gas lasers, typically an excimer laser, and solid-state lasers, typically a YAG laser, are usually used. A technique has been disclosed in JP 2001-144027 A in which solid-state laser oscillation apparatus such as a Nd:YVO4 laser is used to irradiate an amorphous semiconductor film with laser light that is its second harmonic, and a crystalline semiconductor film larger in grain size than conventional ones is formed and used to manufacture a TFT.
However, when an amorphous semiconductor film formed on a flat surface is crystallized by laser light irradiation, the crystal obtained is polycrystal and it is impossible to control neither positions where grain boundaries containing crystal defects are formed nor positions of distortion and cracks caused by volume shrinkage of the semiconductor film, thermal stress with the base, and lattice mismatch which are brought by crystallization.
Therefore, the crystallinity of the channel region of the TFT cannot be controlled and, in the end, the grain boundaries and crystal defects included in the channel region lead to fluctuation in element characteristic between TFTs.
In short, when using laser light irradiation to form a crystalline semiconductor film, the important objective is to control the crystallinity of a channel region of a TFT by controlling positions of grain boundaries.
To attain a high speed operation memory, it is important to improve semiconductor memory cell characteristics as well as TFT characteristics. This is because improvement in TFT characteristics raise the operation speed of peripheral circuits whereas improvement in semiconductor memory cell characteristics enhances drive performance of semiconductor memory cells, thereby increasing the reading speed.
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a high-speed operation semiconductor memory device having a highly reliable non-volatile memory through a TFT and semiconductor memory cell which have no other grain boundaries than twin crystal in their channel regions, which have high field effect mobility, and which are less fluctuated, by creating a semiconductor memory cell structure that does not allow electric field concentration on an active layer end in a channel region and by controlling positions of grain boundaries and crystal defects and positions of cracks.
A structure of a semiconductor memory cell according to the present invention is characterized in that: the memory cell has, on a substrate having an insulating surface, an insulating film in which linear concave portions are formed; an amorphous semiconductor film or a polycrystalline semiconductor film is formed on the insulating film; the semiconductor film is melted, poured into the concave portions of the insulating film, and crystallized to form a crystalline semiconductor film; a surface of the crystalline semiconductor film is etched away so that the thickness of the crystalline semiconductor film, at least a portion thereof where a channel region is to be formed, is equal to or less than the depth of the concave portions; a first gate insulating film is formed and is in contact with the top face of the crystalline semiconductor film; and a floating gate electrode, a second gate insulating film, and a control gate electrode are formed on the first gate insulating film.
A structure of a semiconductor memory device according to the present invention has a memory cell array that is composed of semiconductor memory cells arranged in matrix, and is characterized in that: the memory cell array has, on a substrate having an insulating surface, an insulating film in which stripe pattern concave portions are formed, the stripe pattern concave portions being plural linear concave portions arranged in a stripe pattern, an amorphous semiconductor film or a polycrystalline semiconductor film is formed on the insulating film; the semiconductor film is melted, poured into the concave portions of the insulating film, and crystallized to form a crystalline semiconductor film; a surface of the crystalline semiconductor film is etched away so that the thickness of the crystalline semiconductor film, at least a portion thereof where a channel region is to be formed, is equal to or less than the depth of the concave portions; unnecessary regions of the crystalline semiconductor film are etched away in accordance with arrangement of the semiconductor memory cells; a first gate insulating film is formed and is in contact with the top face of the crystalline semiconductor film; and a floating gate electrode, a second gate insulating film, and a control gate electrode are formed on the first gate insulating film.
Another structure of a semiconductor memory device according to the present invention has a memory cell array that is composed of semiconductor memory cells arranged in matrix, and is characterized in that: the memory cell array has, on a substrate having an insulating surface, an insulating film in which stripe pattern concave portions and inter-stripe concave portions are formed, the stripe pattern concave portions being plural linear concave portions arranged in a stripe pattern, the inter-stripe concave portions connecting the stripe pattern concave portions with one another; an amorphous semiconductor film or a polycrystalline semiconductor film is formed on the insulating film; the semiconductor film is melted, poured into the concave portions of the insulating film, and crystallized to form a crystalline semiconductor film; a surface of the crystalline semiconductor film is etched away so that the thickness of the crystalline semiconductor film, at least a portion thereof where a channel region is to be formed, is equal to or less than the depth of the concave portions; unnecessary regions of the crystalline semiconductor film are etched away in accordance with arrangement of the semiconductor memory cells and connection between the semiconductor memory cells; a first gate insulating film is formed and is in contact with the top face of the crystalline semiconductor film; and a floating gate electrode, a second gate insulating film, and a control gate electrode are formed on the first gate insulating film. In this structure, semiconductor film wires for connecting the semiconductor memory cells are formed from crystalline semiconductor films that are in the inter-stripe concave portions.
Another structure of a semiconductor memory device according to the present invention has a memory cell array that is composed of semiconductor memory cells arranged in matrix, and is characterized in that: the memory cell array has, on a substrate having an insulating surface, an insulating film in which stripe pattern concave portions are formed, the stripe pattern concave portions being plural linear concave portions arranged in a stripe pattern; an amorphous semiconductor film or a polycrystalline semiconductor film is formed on the insulating film; the semiconductor film is melted, poured into the concave portions of the insulating film, and crystallized to form a crystalline semiconductor film; a surface of the crystalline semiconductor film is etched away while a region to become semiconductor film wires for connecting the semiconductor memory cells is masked with a photoresist so that the thickness of the crystalline semiconductor film, at least a portion thereof where a channel region is to be formed, is equal to or less than the depth of the concave portions; unnecessary regions of the crystalline semiconductor film are etched away in accordance with arrangement of the semiconductor memory cells and semiconductor film wires for connecting the semiconductor memory cells; a first gate insulating film is formed and is in contact with the top face of the crystalline semiconductor film; and a floating gate electrode, a second gate insulating film, and a control gate electrode are formed on the first gate insulating film. In this structure, semiconductor film wires for connecting the semiconductor memory cells are formed from crystalline semiconductor films climbing over the inter-stripe concave portions without being etched.
The term semiconductor memory device refers to non-volatile memories such as EEPROM (Electrically Erasable and Programmable Read Only Memory) and flash memory as well as semiconductor devices in general that have these non-volatile memories as their semiconductor memory units. For example, the term includes microprocessors and semiconductor display devices (typically liquid crystal display devices and EL display devices) which have non-volatile memories as their semiconductor memory units, and apparatus to which the microprocessors and the semiconductor display devices are mounted.
An amorphous semiconductor film in the present invention includes, in addition to one that has a thoroughly amorphous structure in a strict sense, one with microcrystal grains mixed, namely, a microcrystalline semiconductor film, and a semiconductor film with a localized crystal structure. Typically, an amorphous silicon film is employed. An amorphous silicon germanium film, an amorphous silicon carbide film or the like may be employed instead. A polycrystalline silicon film is the one obtained by crystallizing one of these amorphous semiconductor films by a known method.
Shown in FIGS. 1A to 1C are a typical structure of a semiconductor memory cell that constitutes the above-described semiconductor memory device of the present invention. FIG. 1A is a plan view thereof whereas FIGS. 1B and 1C are its sectional view in the channel length direction (sectional view of Axe2x80x94Axe2x80x2) and sectional view in the channel width direction (sectional view of Bxe2x80x94Bxe2x80x2), respectively. In the semiconductor memory cell of FIGS. 1A to 1C, a crystalline semiconductor active layer 102, a first gate insulating film 103, a floating gate electrode 104, a second gate insulating film 105, and a control gate electrode 106 are layered on a substrate 101 having an insulating surface. The crystalline semiconductor active layer 102 is formed in a linear concave portion defined by insulating films 109 and 110. The crystalline semiconductor active layer 102 is composed of a channel region 107 and high concentration impurity regions 108 that are doped with an impurity of one conductivity type.
One of the high concentration impurity regions 108 may partially overlap the floating gate electrode 104 with the first gate insulating film 103 sandwiched therebetween.
A semiconductor memory cell of the present invention is characterized in that side faces of a portion of a crystalline semiconductor film that forms a channel region are completely covered with side walls of a concave portion through a step of removing by etching a surface of the crystalline semiconductor film so that the thickness of the crystalline semiconductor film, at least the portion thereof that forms a channel region, is equal to or less than the depth of the concave portion.
As shown in FIGS. 1A to 1C, the crystalline semiconductor active layer may be thinner than the insulating films 109 and 110 or may be as thick as the insulating films 109 and 110.
The above semiconductor memory cell has in section no corner in the interface between the semiconductor active layer and the first gate insulating film and the interface is flat. Accordingly, this semiconductor memory cell is free from the problem of electric field concentration on a semiconductor active layer end which causes local injection/discharge of electric charges. As a result, local degradation of the first gate insulating film can be avoided and high reliability is obtained.
The semiconductor memory device described above may have, on a substrate where memory cells are formed, peripheral circuits such as a decoder circuit for selecting a memory cell and a reading/writing circuit, and other semiconductor integrated circuits. In this case, a crystalline semiconductor film formed by the above-described method is preferably used for TFTs that constitute the peripheral circuits and other semiconductor integrated circuits in order to increase the operation speed of the memory.
The method of forming a crystalline semiconductor film is described furthermore.
The above-described linear concave portion is one of stripe pattern concave portions, and stretches in the channel length direction. The width of the concave portion (corresponding to the channel width in a channel formation region) is equal to or more than 0.01 xcexcm and equal to or less than 2 xcexcm, preferably, 0.1 to 1 xcexcm. The depth of the concave portion is equal to or more than 0.01 xcexcm and equal to or less than 3 xcexcm, preferably, 0.1 xcexcm or more and 2 xcexcm or less.
Employed for a measure to melt and crystallize the crystalline semiconductor film is pulse oscillation or continuous wave laser light from gas laser oscillation apparatus or solid-state laser oscillation apparatus as a light source. The laser light is collected by an optical system into a linear shape before irradiation, and may have such intensity distribution that is uniform in a region in the longitudinal direction while varied in the lateral direction. The laser oscillation apparatus used as the light source is rectangular beam solid-state laser oscillation apparatus, and slab laser oscillation apparatus is particularly preferred.
Laser light or intense light collected into a linear shape and expanded in the longitudinal direction irradiates the amorphous semiconductor film or polycrystalline semiconductor film while the laser light irradiation position and the substrate on which the semiconductor film is formed are moved in a relative manner. By running the laser light over a part of, or the entire surface of the semiconductor film in this way, the semiconductor film is melted and then crystallized or re-crystallized. The laser light scanning direction is parallel to the linear concave portion formed in the insulating film or matches the channel length direction of the transistor. This makes crystals grow along the laser light scanning direction, thereby preventing grain boundaries from crossing the channel length direction.
By setting the depth of the concave portion equal to or more than the thickness of the semiconductor film, the semiconductor melted by irradiation of laser light or intense light gathers in the concave portion through surface tension and solidifies. At this point, crystals are let grow from a bottom edge of the concave portion to make distortion that accompanies crystallization concentrate on other regions than the concave portion. This saves a portion of the crystalline semiconductor film that fills the concave portion from the distortion. The rest of the crystalline semiconductor film, which remains around the concave portion and which contains grain boundaries and crystal defects, is removed by etching.
The semiconductor memory cell manufactured as above has, in a linear concave portion formed on an insulating surface, a crystalline semiconductor film that contains no other grain boundaries than twin crystal.
The present invention described above makes it possible to specify locations of channel formation regions of semiconductor memory cells and TFTs and form crystalline semiconductor films that contain no other grain boundaries than twin crystal in the channel regions. This means that the crystallinity of the channel regions of the TFTs and semiconductor memory cells can be controlled and improved, thereby giving high field effect mobility to the semiconductor memory cells and TFTs and making them less fluctuated in characteristic. Improvement of TFT characteristics increases the operation speed of peripheral circuits and improvement of semiconductor memory cell characteristic increases the reading speed. As a result, a semiconductor memory device that can operate at high speed is obtained.